Circuit design guidelines for n-channel MOSFET hot carrier robustness

Reviews present understanding of the AC stress effect in n-MOSFETs, defining and parameterizing the AC stress model. The authors incorporate the AC hot-carrier model into a circuit-level hot-carrier reliability simulator, ADHOC, that works in concert with SPICE. Sources of on-chip voltage excursions...

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Veröffentlicht in:IEEE transactions on electron devices 1993-07, Vol.40 (7), p.1284-1295
Hauptverfasser: Mistry, K.R., Fox, T.F., Preston, R.P., Arora, N.D., Doyle, B.S., Nelsen, D.E.
Format: Artikel
Sprache:eng
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Zusammenfassung:Reviews present understanding of the AC stress effect in n-MOSFETs, defining and parameterizing the AC stress model. The authors incorporate the AC hot-carrier model into a circuit-level hot-carrier reliability simulator, ADHOC, that works in concert with SPICE. Sources of on-chip voltage excursions above the nominal value of the power supply V/sub dd/ are explored, and this information is used to develop a set of design guidelines at the transistor level. The hot-carrier reliability of a broad class of basic circuit building blocks is then simulated and used as the basis for a comprehensive set of design guidelines at the transistor and circuit levels.< >
ISSN:0018-9383
1557-9646
DOI:10.1109/16.216434