The tree-match chip

A chip organization is proposed for the classical tree-pattern-matching problem. It is based on an algorithm which uses a combination of a content-addressed memory, shift registers, and one-bit-wide stacks. All tree pattern matches are found simultaneously in one scan of the subject stream. The chip could be operated as a coprocessor to speed up functional language processing implementations. Multiple chips can be cascaded to increase capacity, similar to the way in which memory chips are utilized. An example chip has been laid out in CMOS technology in a 40-pin standard frame. Comparisons to previous algorithms are discussed.< >