On the methodology of calculating volume charge density in a MIFGMOS substrate using Poisson’s equation

Purpose This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor. Design/...

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Veröffentlicht in:Microelectronics international 2021-10, Vol.38 (4), p.206-215
Hauptverfasser: Plascencia Jauregui, Francisco Javier, Medina Vazquez, Agustín Santiago, Becerra Alvarez, Edwin Christian, Arce Zavala, José Manuel, Flores Ruiz, Sandra Fabiola
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Sprache:eng
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Zusammenfassung:Purpose This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor. Design/methodology/approach Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths. Findings The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena. Originality/value The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.
ISSN:1356-5362
1758-812X
DOI:10.1108/MI-01-2021-0004