Impact of material properties and device architecture on the device performance for a gate all around nanowire tunneling FET

This paper systematically investigates the impact of gate dielectric, channel dimensional profile and the interface trap charge density on a homojunction indium-arsenide (InAs) gate all around nanowire tunneling FET (HJ-GAA-TFET). Device models were calibrated against the experimental data and simulations were performed to investigate the underlying physics. Device on-off (Ion/Ioff) ratio was considered as key figure-of-merit (FOM) to improve. It is observed that the off current (Ioff) is a weak function of dielectric constant, however, the on current (Ion) increases from 1.51 × 10−7 A µm−1 to 1.79 × 10−6 A µm−1 as the dielectric constant increases from SiO2 to La2O3. It was also observed that as the diameter increases, both Ion and Ioff increases. Ion/Ioff ratio is independent for higher channel lengths but as the channel length is reduced below 30 nm, Ioff increases causing degradation in Ion/Ioff ratio. Finally, the effect of interface traps was realised on the Ion/Ioff ratio. Interface traps impact the flat-band voltage causing a shift in the device performance. It is observed that as the trap density increases, Ioff degrades rapidly by ~3 orders in magnitude.