A MOS capacitor model for ultra-thin 2D semiconductors: the impact of interface defects and channel resistance

In an edge capacitor based on 2D semiconductors, charge transport in the channel leads to frequency dispersion in capacitance and peaks in conductance, which convolutes information from interface defects (Dit). If not careful, Dit can be grossly misinterpreted. In this study we develop a distributed MOS capacitor model that distinguishes between these two effects. We incorporate charge transport in terms of channel resistance and evaluate the impact of interface defects in few monolayers thick (1 − 5 layers) MoS2 channel. Using this, an optimized MOS capacitor geometry is identified. By comparing the model with experimental data, we obtain exponential defect states ( Dit,peak=3−4×1013 cm−2 eV−1, σ = 0.12 − 0.08 eV) originating from the conduction band for MoS2 on 4 nm HfO2 and 21 nm SrTiO3, respectively. The model successfully captures the length dependence of MOS capacitors and the static and dynamic behavior of Dit.