Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source (CSNS), single event upset (SEU) cross sections of 14 nm fin field-effect transistor (FinFET) and 65 nm quad data rate (QDR) static random-access memories (SRAMs) are obtained under different incident directions of neutrons: front, back and side. It is found that, for both technology nodes, the “worst direction” corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume. The SEU cross section under the worst direction is 1.7–4.7 times higher than those under other incident directions. While for multiple-cell upset (MCU) sensitivity, side incidence is the worst direction, with the highest MCU ratio. The largest MCU for the 14 nm FinFET SRAM involves 8 bits. Monte–Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.