Superconducting fault current limiter (SFCL) for a power electronic circuit: experiment and numerical modelling

In this article, the superconducting fault current limiter (SFCL) explores its relatively new application: the power electronic circuit. The investigation of this compact-size SFCL involves both the experiments and numerical modelling. A bifilar-shape resistive-type SFCL was used in a DC-DC power conversion circuit, for the purpose of suppressing the overwhelming fault current by 3 different types of faults: the input fault, output fault, and switch fault. The numerical modelling of SFCL used an electromagnetic-thermal coupled finite-element method (FEM) model based on the H -formulation. For these 3 types of faults with the 100 ms fault duration, good agreement was found between the experiments and simulations. Both the experiment and modelling method were used to test the SFCL performance with different fault durations (50 ms vs 100 ms). For some severe fault conditions (e.g., higher fault current and longer fault duration) that experiments were difficult or unable to realise, the FEM modelling of SFCL was used to simulate the performance. Overall, the FEM modelling of SFCL can well match the SFCL experiment, and has the advantage of showing more information such as the current distribution and temperature. Both the SFCL experiments and numerical modelling offer new results and novel concepts of SFCL investigation, which can be helpful for the design of future SFCLs and the compact protection schemes for power electronic devices.