Design of Ga 2 O 3 Trench Gate MOSFET Devices with Dielectric Pillars

In this study, a β-Ga 2 O 3 U-groove gate metal-oxide-semiconductor field-effect transistor (UMOSFET) with a high breakdown voltage (BV) is proposed. Through TCAD simulation, both forward and reverse electrical characteristics are comprehensively investigated. The integration of traps within the current blocking layer (CBL) is suggested to enable effective current blocking. Furthermore, to optimize the BV, the introduction of oxide dielectric pillars on either side of the drift layer is implemented to enhance the potential distribution during breakdown. The forward and reverse electrical characteristics of the device at different temperatures are also investigated. Additionally, by conducting simulation optimizations of different doping concentrations in the drift layer, CBL layer thickness, and trap concentrations, notable achievements are realized, which include a high BV of 865.2 V, low threshold voltage of 2.587 V, and low specific ON-resistance of 19.2 mΩ·cm 2 . This study presents a novel structural design to foster the potential application and development of Ga 2 O 3 electronic devices.