Dislocation sink annihilating threading dislocations in strain-relaxed Si 1-x Ge x layer

We proposed a dislocation sink technology for achieving Si Ge multi-bridge-channel field-effect-transistor beyond 5 nm transistor design-rule that essentially needs an almost crystalline-defect-free Si Ge channel. A generation of a dislocation sink via H implantations in a strain-relaxed Si Ge layer grown on a Si substrate and a following annealing almost annihilate completely misfit and threading dislocations located near the interface between a relaxed Si Ge layer and a Si substrate. A real-time (continuous heating from room temperature to 600 °C) in situ high-resolution-transmission-electron-microscopy and inverse-fast-Fourier-transform image observation at 1.25 MV acceleration voltage obviously demonstrated the annihilation process between dislocation sinks and remaining misfit and threading dislocations during a thermal annealing, called the [Si or Ge + V or V → Si Ge ] annihilation process, where Si , Ge , V , and V are interstitial Si, interstitial Ge, Si vacancy, and Ge vacancy, respectively. In particular, the annihilation process efficiency greatly depended on the dose of H implantation and annealing temperature; i.e. a maximum annihilation process efficiency achieved at 5 × 10 atoms cm and 800 °C.