The architecture of a highly reconfigurable RISC dataflow array processor

The architectural design and VLSI implementation of a highly reconfigurable dataflow RISC (DF-RISC) processing element (PE) are presented. This processor forms an element of a processor array (DF-RISC-PA) which possesses the features of both static and dynamic dataflow models. The array can be programmed to execute arbitrary algorithms (recursive or irregular) in both static and dynamic manner. The processor array is modelled at the behavioural level in VHDL. The gate level implementation and VLSI layout of both the PE and the array are obtained with the help of OASIS Silicon compiler by translating the VHDL model to Logic3. Sample computations are mapped to illustrate functionality. The design is validated at all levels of abstraction. The results of simulation of the PE array are presented. The architecture is compared with previous approaches. The prototype PE requires 4261 CMOS gates and uses an area of 7512 × 8081 μm 2 .