A systematic methodology for mapping DSP algorithms onto multilevel array architectures

In this paper, a systematic graph-based methodology for designing systolic arrays, which can perform concurrently, is introduced. Partitioning a DSP iterative algorithm into a number of sub-algorithms, we describe each of them, along with their interdependences, with a set of Uniform Recurrent Equat...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:International journal of electronics 1995-11, Vol.79 (5), p.507-518
Hauptverfasser: SOUDRIS, D. J., GEORGAKOPOULOS, P. D., GOUTIS, C.E.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:In this paper, a systematic graph-based methodology for designing systolic arrays, which can perform concurrently, is introduced. Partitioning a DSP iterative algorithm into a number of sub-algorithms, we describe each of them, along with their interdependences, with a set of Uniform Recurrent Equations. Alternative architectures can be designed by mapping the dependence graph of the algorithm onto hardware. The main feature of the proposed architectures is the significant reduction of the computation time of the algorithm.
ISSN:0020-7217
1362-3060
DOI:10.1080/00207219508926288