Pregenerated count-enable counters

A technique for implementing counters, with a minimum period equal to the delay of one gate plus the delay of one flip-flop, is described. This technique is based on the concept of the pregenerated count-enable, which is presented first. Then, we apply the concept in the implementation of counters o...

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Veröffentlicht in:	International journal of electronics 1993-06, Vol.74 (6), p.939-944
Hauptverfasser:	PEKMESTZI, K. Z., THANASOURAS, N.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Electronics Exact sciences and technology Integrated circuits Integrated circuits by function (including memories and processors) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Online-Zugang:	Volltext
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Beschreibung
Zusammenfassung:	A technique for implementing counters, with a minimum period equal to the delay of one gate plus the delay of one flip-flop, is described. This technique is based on the concept of the pregenerated count-enable, which is presented first. Then, we apply the concept in the implementation of counters of any length. Finally, we make comparisons between the proposed and conventional design techniques.
ISSN:	0020-7217 1362-3060
DOI:	10.1080/00207219308925896