Design and simulation of a high reliability non-volatile CMOS EEPROM memory cell compatible with scaling-down trends

A simple but high-reliability non-volatile electrically-programmable and erasable memory cell (EEPROM) based on a non-avalanche injection mechanism is presented. This memory cell is composed of a double gate CMOS inverter. Circuit design allows fast programming and erasing (t b < 20 ms) with a single supply voltage of 5 V (at MOSFET channel length L = 2 um and width = 20 μ). It employs a non-avalanche injection mechanism which guarantees a minimized oxide and interface degradation which leads to higher reliability and better operation stability. The EEPROM circuit latches the input data owing to the bidirectional hot carrier gate current. In this EEPROM, the majority of drawbacks of recent memories such as poor stability, long programming time, low reliability and the necessity of using two power supplies are removed. We then introduce a powerful simulation technique to compute V 0 (t), the output voltage, during programming and erasing cycles and also the programming time t b Computations have indicated good compatibility of the present EEPROM with the recent scaling-down trends in VLSI technology.