Electron mobility increase in submicronic transistors integrated on ultrathin silicon membranes subjected to high mechanical stress

In this contribution we investigate an original method to apply high values of biaxial stress: The integration of submicronic fully depleted silicon on insulator transistors on ultrathin silicon membranes. The membranes are micromachined in the device substrate, the buried oxide facilitating the control of the membrane thickness below 1 μ m . High values of biaxial stress can thus be applied on the transistor channel without the drawbacks of conventional methods. The experimental results obtained using 750 nm thick membranes are presented. The piezoresistive longitudinal coefficient obtained for strained silicon on insulator wafer ( 240 × 10 − 12 Pa − 1 ) is in good agreement with the results obtained by the four-probe bending method.