Graphene field effect transistors with parylene gate dielectric

We report the fabrication and characterization of graphene field effect transistors with parylene back gate and exposed graphene top surface. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted optical reflection microscopy to be used for identifying exfoliated graphene flakes. Room temperature mobilities of 10 000 cm 2 / Vs at 10 12 / cm 2 electron/hole densities were observed in electrically contacted graphene. Parylene gated devices exhibited stable neutrality point gate voltage under ambient conditions and less hysteresis than that observed in graphene flakes directly exfoliated on silicon oxide.