Multibit memories using a structure of SiO2/partially oxidized amorphous Si∕HfO2

Memory capacitors with a structure of SiO2/partially oxidized amorphous Si (a-Si)/HfO2 have been prepared by sequential processes: atomic layer deposition (ALD) of 6nm a-Si on 3.5nm SiO2, thermal oxidation at 900°C, and another ALD of 12nm HfO2. The memory devices offer hybrid type of charge memory: the interface states of partially oxidized a-Si∕SiO2 tend to act as hole traps, resulting in a negative shift of flatband voltage in capacitance-voltage (C-V) curve, and the partially oxidized a-Si∕HfO2 interface has dominantly electron-trap centers, leading to a positive voltage shift. By this hybrid effect, the memory window in C-V curve is observed to be enlarged enough to realize four-level (2bit) memories, which is demonstrated through measurements of program/erase speeds and charge-loss rates.