Electron mobility in double gate silicon on insulator transistors: Symmetric-gate versus asymmetric-gate configuration

We have studied electron mobility behavior in asymmetric double-gate silicon on insulator (DGSOI) inversion layers, and compared it to the mobility in symmetric double-gate silicon on insulator devices, where volume inversion has previously been shown to play a very important role, being responsible for the enhancement of the electron mobility. Poisson’s and Schroedinger’s equations have been self-consistently solved in these structures to study and compare the distribution of the electrons. We show that the lack of symmetry in the asymmetric DGSOI structure produces the loss of the volume inversion effect. In addition, we show that as the silicon thickness is reduced the conduction effective mass of electrons in asymmetric devices is lower than that in the symmetric case, but that the greater confinement of electrons in the former case produces a stronger increase in the phonon scattering rate, and in the surface roughness scattering rate. We have solved the Boltzmann transport equation by the Monte Carlo method, and have evaluated the electron mobility. The electron mobility curves in asymmetric DGSOI devices are shown to be considerably below the mobility curves corresponding to symmetric devices, in the whole range of silicon thicknesses. The difference is greater in the range 5–25 nm, where electron mobility in symmetric DGSOI inversion layers is greatly improved by the volume inversion effect. We show that mobility in symmetric devices could be 2.5 times greater than that for their asymmetric counterparts.