Synthesis and the new physics

Software tools based on synthesis that are indispensable to modern chip design are struggling to cope with the demands of nanometre scale geometrics. The first attempt to fix these problems was to add a physical synthesis step after register-transfer level (RTL) synthesis. But this approach often created unroutable designs due to lack of prediction about where real wires were likely to go. Next came virtual prototyping, the idea being to produce a fully functional and physically feasible chip layout including wire routing, eg, the Cadence First Encounter RTL-to-GDSII flow. Other approaches include gain-based synthesis from Magma and Precision Physical Synthesis from Mentor Graphics. The EDA industry could be said to be "getting there" but deep submicron design is never going to be straightforward. New problems continue to appear - crosstalk between wires, power leakage, power consumption, and yield problems caused by bad positioning of circuit structures.