Transfer Learning-Based Artificial Intelligence-Integrated Physical Modeling to Enable Failure Analysis for 3 Nanometer and Smaller Silicon-Based CMOS Transistors

Integral to the success of the semiconductor industry in keeping up with Moore’s law is the importance of failure analysis (FA). Accurate and fast FA is vital in ensuring yield, reliability, and rapid production in the semiconductor industry. However, locating defects among tens of billions of transistors packed in the tiny modern microchip is not a trivial task. Not only the process technology has to achieve such high integration of devices evolved to become astoundingly sophisticated but also debugging for defects in these chips has become remarkably complex. With electrical nanoprobing, we show how artificial intelligence-integrated physical modeling can be effective in finding difficult proverbial needle-in-a-haystack defects based on the electrical responses of the devices. Moreover, the information learned on current devices can be transferred to the latest transistor technologies, enabling machine learning-based defect sleuths of the future. Notably, we achieved a defect region classification accuracy of 99.5% on well-studied fin nanoscale field-effect transistors (FET) using a defect dataset based on an experimentally calibrated TCAD digital twin model and an adaptive boundary refinement technique. With transfer learning, a defect region classification accuracy of 99.58% is also achieved on the next-generation gate-all-around FETs, overcoming the lack of crucial datasets and optimized labels to guide and accelerate the production process of emerging devices. The proposed technique is expected to be the next level of defect identification, an important stepping stone to accelerate the production process for advanced technology nodes beyond 3 nm.