A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic

Adders are critical to the efficiency of arithmetic circuits in battery-powered electronic devices. This study demonstrates an 8-bit CLA (carry look-ahead adder) using single-phase ANT logic to increase the computation speed and reduce the power dissipation simultaneously. The single-phase ANT has no internal loop that optimizes the efficiency of the prior ANT. Utilizing a TSMC 40-nm technology, the proposed 8-bit CLA is fabricated. It attains the highest operating frequency of 3.2 GHz and the lowest normalized PDP (power delay product) by on-silicon measurement for 20 pF load. [Display omitted] •The CLA uses single-phase ANT logic.•Operating frequency is 3.2 GHz.•For a 20 pF load, Normalized PDP is as low as 0.125 nJ.•For a 20 pF load, Normalized Power is as low as 0.292 mW.•Implemented using TSMC 40-nm CMOS Process on a single chip, with an area of 0.641 mm2 .