A rail-to-rail high speed comparator with LVDS output in 0.18-μm SiGe BiCMOS Technology

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level VC, the overdrive recov...

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Veröffentlicht in:Integration (Amsterdam) 2024-07, Vol.97, p.102198, Article 102198
Hauptverfasser: Sun, Qiyan, Tu, Ruiyong, Xie, Jin, Gong, Yihong, Wu, Sini, Li, Jinghu, Luo, Zhicong
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Sprache:eng
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Zusammenfassung:Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level VC, the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator’s gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator’s output is transmitted at high speed through an LVDS interface. This design is implemented using 0.18μm SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns. •The input common-mode range is expanded to rail-to-rail.•The propagation delay under small input overdrive is greatly reduced.•The static power consumption of the comparator is 26.4 mW.•The comparator’s output is transmitted at high speed through an LVDS interface.•The comparator is implemented using 0.18 μm SiGe BiCMOS technology.
ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2024.102198