LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS

•Design of a new approximate full adder cell by CMOS technology.•Design of a 4-bit carry ripple adder structure.•To measure the circuits’ efficiency at transistor level, the simulations are performed in HSPICE with the 32 nm technology process to assess the power, delay, PDP at different voltages, different temperatures, and different load capacitors.•To implement image multiplication application and to compute error parameters and other analytic parameters MATLAB is applied.•Concluding remarks In this article, a low power, area-efficient full adder cell designed with approximate outputs is presented. The static Complementary Metal Oxide Semiconductor (CMOS) structure is applied to design this approximate full adder energy efficient (up to 72% improvement). The proposed cell simulated in HSPICE with 32nm CMOS technology in four different scenarios. First, the proposed cell was assessed as a 1-bit full adder cell; second, the proposed cell applied in a 4-bit carry ripple adder structure. In the third and fourth scenarios, the proposed cell's power consumption and performance were assessed in different power supply voltages, temperatures, and a larger load capacitor. Approximate computing is a design paradigm that is applicable in image processing as an error-resilient application. MATLAB exploited to assess the proposed approximate full adder in image addition application in three different scenarios. The outputs evaluated by different image quality metrics (such as peak signal to noise ratio (PSNR)) and the final outputs of approximation are acceptable in this application due to image quality metrics.