Boosting the capacity of driving the drain current of the FinFET by a simple changing of the CMOS ICs manufacturing process

•A simple change of the channel manufacturing processes to implement FinFETs, focusing on boosting their drain currents (IDS).•The GiD-FinFETs IDS with a β equal to 45° are 32% higher than those observed in the conventional FinFET counterpart.•The Weff of the GiD-FinFETs is 41.5% larger than that observed in the traditional FinFET counterpart.•By changing the β between the gate and Fin regions, we can boost the FinFETs IDS and its current driver.•The GiD-FinFET aims the reduction of the number of Fins that must be put in parallel to define a specific IDS and their occupied die areas. This work proposes a simple change of the channel CMOS ICs manufacturing processes to implement FinFETs, focusing on boosting their capacity to drive electrical drain current (IDS) concerning the Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) manufacturing process. Called “Gate-in-Diagonal Fin Field Effect Transistor (GiD-FinFET)”, it was carefully designed to ensure its gate region is non-orthogonal to the Fin, as is observed in the standard Fin Field Effect Transistor (FinFET) counterpart. Three-dimensional (3D) numerical simulations were done using the Atlas Semiconductor Devices Simulator from Silvaco Co. to quantify the influence of the angle between the gate and Fin regions (β) in the drain to source current, compared to the one observed in the conventional FinFET counterpart, considering that these devices present the same Fin volumes. The main results found show that the GiD-FinFETs IDS with a β equal to 45° are 32 % (Triode Region: for VGS = 1.0 V and VDS equal to 0.5 V) and 33 % (Saturation Region: VGS equal to 1.2 V and VDS equal to 1.5 V), respectively, higher than those observed in the conventional FinFET counterpart. This can be justified mainly because the effective channel width of the GiD-FinFETs is 41.5 % larger than that observed in the traditional FinFET counterpart, which leads to better use of its Fin region for the conducting IDS concerning the one measured in the conventional FinFET. Therefore, based on these results, by changing the β between the gate and Fin regions, we can boost the FinFETs IDS and consequently their abilities to buffer electrical current, aiming the reduction of the number of Fins that must be put in parallel to define a specific IDS and their occupied die areas.