Analysis of trap distribution and NBTI degradation in Al2O3/SiO2 dielectric stack

•The thin Al2O3/SiO2 as gate dielectric stack is a good candidate to replace SiO2 in CMOS technology node 65 nm and beyond.•The trap state density and energy level distribution in the silicon bandgap are extracted by conductance method.•The selection of the fabrication process optimizes the interface trap density and dielectric reliability (NBTI) of thin Al2O3/SiO2 gate dielectric stack. In this work, p-substrate MOS capacitors with plasma-enhanced atomic-layer-deposited Al2O3/ thermally-grown SiO2 dielectric stack (with a target equivalent oxide thickness of 4.2 nm) are investigated by means of the conductance method in a temperature range from 25 °C to 150 °C. The trap state density and energy level distribution in the silicon bandgap are extracted over the bandgap. Furthermore, negative bias temperature instability is analyzed by two-point capacitance–voltage characterization to evaluate the electrical stability and dielectric reliability of the Al2O3/SiO2 stack. The contributions from interface and oxide trap generations are detailed. Our results indicate that plasma-enhanced atomic layer deposited Al2O3 on thermal SiO2 stack features low interface trap density, and comparable dielectric reliability to conventional SiO2, SiOxNy, and high-k dielectric stacks.