Fabrication and optimization of aggressively scaled Dual-Bit/Cell Split-Gate Floating-Gate flash memory cell in 55-nm node technology

•An length-scaled NORD flash had been fabricated with a bit size of 0.064 µm2.•The SG-channel was scaled down to sub-60 nm with a gate oxide of 115 Å.•A dual-pocket scheme and a novel cell structure were proposed to optimize the scaled cell.•The reading biases were optimized and discussed to enlarge the window of IR10-IR01.•The reliability characteristics and disturb effects were also illustrated and discussed for this scaled cell. An aggressively scaled triple self-aligned split-gate floating-gate (FG) NOR-type Dual-bit/cell (NORD) flash cell was studied and fabricated at 55-nm node technology. Both FG- and selected-gate (SG-) length, for the first time, were scaled down to sub-80 nm and sub-60 nm in NORD flash, respectively. In this paper, performance of aggressively scaled cells were demonstrated by measurements. Firstly, the cell’s characteristics were presented by discussing FG- and SG-transistor’s drain-induced barrier lowering (DIBL) effects and SG-FG coupling effect. It was experimentally revealed that excellent immunity of DIBL effect was still obtained in this highly scaled SG-transistor due to the fully isolated SG-channel. Then, optimization from process for FG-transistor had been discussed. It was shown that the properties of subthreshold region of FG-transistor has been improved by introducing dual pocket implants for the half-isolated FG-channel. Thirdly, reading biases were also studied to expand the window of read currents. A novel cell structure was also proposed to further improve the aggressively length-scaled NORD flash cell without sacrificing bit-area. Finally, the reliability characteristics were also presented.