Pragmatic Z2-FET compact model including DC and 1T-DRAM memory operation

•In this work, we have used detailed DC TCAD simulations to explain the complex variations of current and electrostatic potential in different regions of the S-Shaped ID -VD curve.•The Z2-FET is actually the consequence of electrostatic coupling between two pseudo-diodes: N-type Gated region & P+ Drain diode (governed by positive front-gate bias) and P-type Ungated region & N+ Source diode (controlled by negative back-gate bias).•We proposed a surface potential approach (including an empirical formulation of Quasi-Fermi Level) to calculate VON and VOFF, which are the key parameters of our model.•Following the implementation in Verilog-A, parameter extraction has successfully been performed on experimental data and TCAD simulations.•Finally, we extended the voltage-current model to 1T- DRAM application.•Our approach consists in shifting VON in accordance with the memory state through an equivalent circuit.•This pragmatic DC and memory model allows further investigation of the design to optimize Z2-FET performances, especially at circuit level. Z2-FET, a partially gated diode, was explored for Electrostatic Discharge (ESD) protection. Its sharp switching behavior is also promising for single-transistor (1T-DRAM) memory application. Based on detailed TCAD simulations, we develop a pragmatic SPICE compact model, including DC and memory operation. The model is validated via TCAD and experimental data. The proposed model reproduces the S-shaped V-I characteristics, the hysteresis and the turn on/off voltages. This model is implemented using Verilog-A and allows to evaluate, through SPICE simulation, the figures of merit for DC, transient and memory operation. It is useful for cell optimization and memory matrix design.