The future of bent MAPS, full-wafer (stitched) design: Status and challenges

CMOS Monolithic Active Pixel sensors (MAPS) have been undergoing significant advances over the last decade in terms of integration densities, radiation hardness and speed. They became the technology of choice for precise vertex detectors at high energy physics experiments with moderate radiation loads, notably STAR at RHIC, ALICE at LHC, and are being considered for future FCC-ee detectors. Being based on commercial CMOS imaging processes, MAPS naturally benefit from the fast progress in the field of commercial imaging. In particular, smaller feature sizes and larger wafers are becoming available now; 65nm on 300mm wafers are for instance available in the Tower Partner Semiconductor CMOS imaging technology. Typical sensitive layer thicknesses are 30 μm or even less, depending on the technology, allowing overall thickness of only 50 μm. At those thicknesses, the sensors become flexible enough to be bent into truly cylindrical shapes down to radii below 2cm. Together with a processing option called stitching, it is possible to produce sensors of wafer scale, making it possible to build real detector half-cylinders out of single sensors, which brings down the material budget to a minimum. This contribution will showcase the state of the art of wafer-scale, bent MAPS, detail the design challenges, report on first results from prototype circuits, and outline the next steps to make technology available for the first applications. In particular, a number of recent results from a first prototype run with two different 26cm long MAPS, which were developed in the context of the CERN EP R&D programme together with ALICE, will be given. •Development of truly-cylindrical, wafers-size detectors.•Design and first production of stitched MAPS in a 65 nm CMOS process.•First results of 26 cm long, stitched sensors.•Bending of 50 μm thick wafer-size sensors to radii below 2 cm.