An FPGA-based 48-channel, 250 mega samples per second throughput time measurement system

Field programmable gate array (FPGA)-based time-to-digital converters (TDCs) have been developed for years, which are widely used in high-energy physics, nuclear medical imaging and so on. In an application with large amount of channels and great destructiveness, TDC-based time measurement system should be optimized for real-time sampling and high data rate transmission when it is implemented in FPGA. In this paper, an FPGA-based 48-channel, 250 mega samples per second time measurement system is presented. A sampling controller is designed to overcome the length variation of carry chains. The sampling controller enables each carry chain to be distributed in one clock domain, which avoid the ultra-wide bins between different clock domains. Inner FIFOs are used to realize real-time sampling in a finite time, which can record every valid sampling with a dead time of 2 ns. Gigabit transceivers are utilized to support 10-Gb/s data transmission. Test results show that the average RMS resolution is about 16.4 ps.