A fully integrated 10-bit 100 MS/s SAR ADC with metastability elimination for the high energy physics experiments

This paper presents a fully integrated 10-bit 100 MS/s successive approximation register (SAR) ADC for the high energy physics experiments. The ADC uses a non-binary weighted capacitor digital-to-analog converter (C-DAC) network and a hybrid capacitor switching procedure to increase conversion accuracy and speed. A metastability elimination technique is employed to avoid comparator metastability, and then reduce the conversion error rate (CER) at high-speed asynchronous operations. The full custom static logic is used to improve the radiation hardness. The ADC was designed and fabricated in a 40 nm CMOS process. It occupies 0.078 mm2 active area, including a reference generator, with a core area of 0.037 mm2. The measured ADC core power consumption and the total power consumption are 1.32 mW and 8.5 mW respectively, including the reference generator at a 1.1 V supply. The resulting figure-of-merit (FOM), for sampling rate 100 MS/s, is 130 fJ/conversion-step. It achieves a good dynamic performance with ∼9.3-bit effective number of bits (ENOB) at 100 MS/s with 14.97 MHz input signal. The measured spurious free dynamic range (SFDR), total harmonic distortion (THD) and signal-to-noise ratio (SNR) are 72.6 dB, −69.2 dB, 58.3 dB, respectively. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.62/−0.4 LSB and +0.67/−0.54 LSB respectively.