Systematic exploration of N-bit Vedic multipliers: A roadmap of technological approaches in pursuit of future trends

This review article presents a systematic exploration of N-bit Vedic multipliers, focusing on the technological approaches utilized for their front-end and back-end stage implementations. It highlights the diverse simulation tools employed in both stages to develop efficient multiplication units, including the use of hardware description languages for the front end and schematic design with functional verification for the back end stage. Vedic multipliers are becoming increasingly popular as efficient multiplication units, with the latest advancements employing CMOS and Quantum Dot Cellular Automata (QCA) technologies. However, CMOS technology has several limitations in terms of physical, material, power-thermal, technological, and economic factors, leading to the development of QCA as a promising nanotechnology. The article discusses the paradigm shift from CMOS to QCA technology and its benefits and implications. Additionally, the article provides a systematic classification of the diverse application areas where Vedic multipliers are used. By exploring the potential aspects of Vedic multipliers and delving into the technological shift towards QCA, this review article offers valuable insights into their implementation and highlights the vast range of potential applications they may revolutionize.