Elimination of splash damage for smaller scribe widths in next-gen memory devices via stealth dicing

Scattered light damage (splash) is one of the common defects that can be observed from the stealth dicing process, and it is mainly due to the interaction of the pulsed laser beam with the micro-crack and modified layer formed. This might cause thermal damage on the active layer of the die and degrade the reliability and yield of the device. The development of new technology node for memory devices aims to reduce scribe width, thereby increasing the number of dies per wafer. The ongoing trend towards scribe width reduction from 120 μm to current sub-60 μm, results in increased throughput and decreased cost per die. Furthermore, this reduction allows for greater functionality integration within a confined space, thereby enhancing overall device performance. Hence, the elimination of splash during the SD process is imperative to enable further shrinking of scribe width. This paper focuses on the impact of pulse pitch and distance from 1st focal depth to silicon (Si) frontside on the maximum splash distance. Lower pulse pitch and lower distance from 1st focal depth to Si frontside will introduce higher splash distance. An empirical model for splash elimination was established to determine the critical distance from 1st focal depth to Si frontside as a function of pulse pitch.