Scattering suppression at MOS interface towards high-mobility Si-based field-effect transistors

The severe scattering at metal-oxide-semiconductor (MOS) interfaces, manifesting as carrier mobility declining, is always a puzzle in the field of Si-based field-effect transistors (FETs) towards high-performance devices. In this work, an elaborate study on interfacial scattering suppression through process optimization is reported. Dry oxidation is proved to be more efficient in the construction of a damage-free oxide/semiconductor interface. Meanwhile, a thick thermal-SiO2 interlayer (i.e. a long growth time), together with a long-duration post-annealing treatment, is beneficial for interface planarization. Such an interface roughness scattering control, combined with Coulomb and defect scattering restrictions, can be realized with an optimized FET process flow. On this occasion, the as-fabricated Si MOSFETs show a higher gate-controlled drain current, and are with a peak electron mobility of ∼8372 cm2 V−1 s−1 at 1.6 K. Moreover, confined magnetotransport properties of two-dimensional electron gas are further revealed by the integer quantum Hall effects. Notably, our work presents a feasible integration flow to fabricate high-mobility Si MOS devices via scattering suppression, which may promote the evolution of Si-based MOS quantum dots for potential solid-state quantum computing. [Display omitted]