Borophene vertical dopingless Tunnel FET with high-κ dielectric and incorporating gate–drain underlapping technique

Tunnel-FETs are ideal for low-power electronic applications, particularly in areas requiring steep subthreshold slope and energy-efficient switching. However, traditional TFETs face major issues, including low ON-current (ION), random dopant fluctuations, and ambipolar conduction, which limit their performance and scalability. To address these issues, this study proposes the novel design of a borophene-based vertical dopingless TFET, incorporating a gate–drain underlapping (GDU) technique. The study employs high-κ dielectrics, specifically HfO2, to improve electrostatic control within the device. Through extensive analysis and optimisation, the proposed device, featuring a 1nm HfO2 dielectric, achieves a remarkable subthreshold swing of 8.44mV/dec and an impressive ION of 2.45×10-4A/μm at a drain bias of 0.5V. The GDU technique effectively suppresses ambipolar conduction and reduces gate-to-drain capacitance, significantly improving device performance. By leveraging borophene’s unique properties and the novel vertical dopingless architecture, this work advances the design of TFETs. •Achieves 8.44 mV/dec subthreshold swing and 2.45 × 10-4A/μm ON-current.•Gate–Drain Underlapping suppresses ambipolar conduction and reduces Cgd.•1nm HfO2 dielectric boosts ON-state performance in device simulations.•Advances TFETs for low-power electronics with borophene’s unique properties.