Hardware Implementation of Effective Framework for the Trade-off between Security and QoS in Wireless Sensor Networks

The trade-off between security and quality of service (QoS) in wireless networks has attracted great attention in recent years. This paper presents a hardware implementation of a novel framework for realizing the trade-off between security and QoS in wireless sensor networks (WSNs) regarding the hos...

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Veröffentlicht in:Microprocessors and microsystems 2022-09, Vol.93, p.104590, Article 104590
Hauptverfasser: Abdul-Karim, Mona Sayed, Rahouma, Kamel Hussien, Nasr, Khalid
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Sprache:eng
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Zusammenfassung:The trade-off between security and quality of service (QoS) in wireless networks has attracted great attention in recent years. This paper presents a hardware implementation of a novel framework for realizing the trade-off between security and QoS in wireless sensor networks (WSNs) regarding the hostility of the operating environment and the available resources of our objects. For evaluating the hostility of the operating environment, we developed an effective intrusion detection unit that sends an alarm signal to a control unit that also collects the data-carrying information about the available resources. As our work is concerned with WSNs, we focus on the power consumption of sensor nodes as the considered object resources. According to the collected data from the intrusion detection unit and resources status unit, the control unit can evaluate the situation of the object in the operating environment and sends control signals to a security unit to select the appropriate level of security among three levels (low, medium, and high) available in our developed framework. The three security levels consider different combinations of the cryptographic algorithms Hash-based Message Authentication Code (HMAC) and Advanced Encryption Standard (AES), with different key lengths, regarding the required security services (confidentiality, authentication and integrity) and available resources. To reinforce the QoS, we considered the advantages of hardware implementation in addition to maintaining the object resources. Our framework has been implemented using Field Programmable Gate Array (FPGA), Virtex-7 (xc7v585tffg1761–3), which helps in achieving reasonable performance with a maximum operating frequency of 206.838 MHz and throughput of 2.3 Gbps.
ISSN:0141-9331
1872-9436
DOI:10.1016/j.micpro.2022.104590