High-throughput energy-efficient pipeline architecture for successive cancellation polar decoder

Polar codes are a class of block channel coding that can theoretically achieve channel capacity. The Polar codes are used in 5G applications due to superior error correction performance. Throughput and energy efficiency are important issues for efficient hardware implementation of Polar codes in real-world applications. This paper presents a high-throughput and energy-efficient pipeline architecture for a fast simplified successive cancellation decoding algorithm. In this architecture, the searching method in the Polar code data bit positions is improved which leads to ignoring computing all of the bits in the ordinary approach. This results in having efficient length for each node type which can make a tradeoff in latency and T/P. Furthermore, the supernode which helps to decrement the latency of the decoder are discussed and used to improve the decoder. Utilizing the supernodes, the number of pipeline stages decreases with a negligible corruption in the maximum frequency and throughput. The Polar decoder is implemented on Xilinx kintex-7 xc7k325t-2ffg900c. The achieved number of pipeline stages is 118 and the maximum clock frequency is 284 MHz on the target FPGA chip. The throughput of the decoder is up to 290.81 Gb/s and the latency is 415ns. The energy per bit is 3.14 pJ/bit. The implementing results confirm that the proposed decoder significantly improves the throughput and energy per bit in comparison with the related pipeline decoders.