A power-efficient, single-phase, contention-free flip-flop with only three clock transistors

Flip-flop research in recent years has been motivated by power- and/or energy-efficient designs. Flip-flop power is based on data activity (DA), which in many applications ranges from 5 to 15%. In such cases, a substantial amount of clock power and energy is wasted. In this paper, a power-efficient, contention-free flip-flop with only three single-phase clock transistors is proposed, which has low-power consumption and eliminates unnecessary internal transitions in the circuit. This flip-flop is referred as 3CTSPC. Test-chip measurement results show that at VDD = 1 V, CK = 25 MHz, and DA = 12.5%, 3CTSPC is 11% and 58% more power-efficient than 18TSPC and TGFF, respectively.