Single-event burnout hardening evaluation with current and electric field redistribution of high voltage LDMOS transistors based on TCAD Simulations

—A single-event burnout (SEB) hardened design based on high voltage lateral double-diffused metal-oxide-silicon (LDMOS) devices with an optimal partial buried oxide (BOX) layer and a N-buffer layer is firstly proposed in this paper. By analyzing the response of surface electric field and transient current, the optimal parameters of hardened layers are selected. Simulation results reveal that an optimal buffer layer can suppress the peak electric field from 4.5 MV/cm to 2 MV/cm, recreate the position of peak electric field and an optimal BOX layer can reconstruct the path of electron and hole currents, reducing the risk of parasitic bipolar-junction-transistor (BJT). By contrast, the SEB triggering voltage can be improved from 197 V to 396 V, with an increase of 100%. And the ratio of safe operating area (SOA) with SEB to breakdown voltage (BV) can be increased from 30% to 69%. In the case of heavy-ions with different energies, the SEB hardened LDMOS also has better performance than the conventional one.