A 16-bit 2.5-MS/s SAR ADC with on-chip foreground calibration

This article presents a 16-bit 2.5-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with on-chip foreground calibration, including two digital-to-analog converters (DACs). Apart from the traditional segmented capacitor DAC (CDAC) used in ADC, the assistant DAC (ADAC) is added to store errors, including offset and mismatch, and compensate them based on the calculation. The high-performance comparator and modified timings are used to meet the needs for speed and resolution while paralleling switches are applied to reduce the impacts of charge injection. The proposed SAR ADC has been designed and fabricated in a 55 nm CMOS process with an area of 0.76 mm2. The 81.51 dB signal to noise-plus-distortion ratio (SNDR) and the 96.8 dB spurious-free dynamic range (SFDR) are measured at 2.5 MS/s respectively, while the integral nonlinearity (INL) is ＋2.4/−1.7 LSB. The core ADC consumes 25.8 mW power under 3.3 V analog supply and 1.2 V digital supply with the Schreier figure-of-merit (FOMs) 159.8 dB.