Design and FPGA implementation of a multirate Δ∑ time-to-digital converter with third-order noise-shaping

This paper presents a third-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC). An FPGA development board of Altera Stratix IV was used to implement the prototype of the proposed TDC. Multirating technique is employed in this work to improve the performance over conventional TDCs. Measured results demonstrate considerable influence of multirating technique on enhancing signal-to-noise ratio (SNR), from 50.68 dB in single-rate mode to 64.8 dB in multi-rate mode (a gain of 14.12 dB). Different sampling clocks and Gated Switched-Ring Oscillators (GSROs) operating frequencies are generated utilizing built-in clock circuitries of the FPGA board. Thus, no discrete sources are needed for measurement by the proposed TDC. Moreover, the proposed design yields low complexity and power consumption since it does not consist of any calibration block and loop. Experimental results of this work and comparing them with state-of-the art Δ∑ TDCs prove that the proposed 1-1-1 MASH TDC can be incorporated in accurate and fast applications such as biosensors and ADPLLs.