High resolution time-to-digital converter using low resources FPGA for time-of-flight measurement

This paper presents the design and implementation of time–to-digital Converter (TDC) with a low-cost, wide dynamic range, with a measurement precision of a few picoseconds. Because of these requirements, the focus of this work is mainly on TDC architectures based on the Nutt interpolation method, which has several advantages when a long measurement range is needed. This technique consists of coarse measurement using a phase-locked loop clock and a fine measurement using two ring oscillators having a slightly different frequency. Best Place and Route delay and loading oscillators with buffers loads are done to get high resolution. To prove the functionality, the new TDC design is implemented at a low cost, low power Xilinx Virtex-5 with device xc5vfx70t-1ff11360f ML507 field-programmable gate array (FPGA). The presented new approach achieved high-resolution TDC of 14ps and a wide dynamic range limited by the 10-bit counter.