Subthreshold read operations in 3D PCM: 1S1R device modeling and memory array analysis

3-D phase change memory (PCM) is one of the most promising next-generation nonvolatile memory, and the subthreshold sensing strategy can effectively improve its limited endurance. In this study, we propose a one-selector-one-resistor (1S1R) model with Monte Carlo (MC) function and provide array configurations for the worst case and the maximum bit line voltage (VBL-max), respectively. Based on these, the read window margin (RWM) is evaluated with various array sizes, OTS threshold voltage variations (σvar), and bias voltages (VBias). Our results reveal that the RWM increases as the VBL approaches the VBL-max. Larger arrays lead to an increased leakage current difference, while larger σvar values result in decreased cell current difference and VBL-max. The decrease in VBL-max further deteriorates the RWM. Additionally, we analyze the optimal VBias for 2-deck arrays achieves a 7% reduction in leakage energy consumption and a 22.6% increase in RWM compared to the V/2 bias. The optimal VBias depends on OTS devices and array sizes. [Display omitted] •A physics-based 1S1R MC model.•Array configurations for worst-case read margin window (RWM).•Array configuration for the maximum bit line voltage (VBL-max).•Higher σvar decrease cell current difference and VBL-max, worsening RWM.•The optimal VBias performs better compared to conventional V/2 bias.