Graph based heterogeneous feature extraction for enhanced hardware Trojan detection at gate-level using optimized XGBoost algorithm

•Adoption of a multifaceted heterogeneous feature extraction approach encompassing structural features, functional features, and graph centrality measures (GCM) based features to handle discrepancies between training and testing data.•The proposed heterogeneous feature extraction process maximizes Trojan space exploration such that a wide variety of Trojans ranging fromsequential, combinational, and always on Trojancan be handled.•The adoption of graph-based features helps to exhibit generalization by enabling the uniform mapping of circuits with similar functionality, irrespective of its logical realization.•The development of the model with mutual information-based features maximizes the projection of Trojan presence.•Leveraging an adaptive information-based synthetic data generation with hybrid sampling to prevent overlap of generated synthetic samples and loss of relevant information.•The development of genetic algorithm-based hyper-parameter optimization to generate an XGBoost model for improved Trojan detection. The requirement of reduced production costs in the domain of integrated circuit(IC) manufacturing and constrained time-to-market are met at the cost of a plethora of security concerns in chip design. In the fourth industrial revolution, where system-on-chip forms the backbone of various electronics, malicious hardware modules known as hardware Trojans within the third-party intellectual property impose a significant security threat. The flexibility and ease of intrusion provided in the earlier stages of design, known as the pre-silicon stage, make it vulnerable to these hardware attacks. Such a scenario further emphasizes the need for effective pre-silicon detection schemes. Since this stage is more vulnerable to hardware attacks. Most existing pre-silicon schemes rely on domain knowledge for feature extraction to develop knowledge-driven but exhibit limited Trojan space exploration. Hence, a proposal that comprises four major stages, viz., multifaceted heterogeneous feature extraction, dynamic hybrid sampling, mutual information-based feature selection, and genetic algorithm-based optimization, has been attempted to handle the challenges. Experimentation on TRIT-TC benchmark circuits resulted in a better predictive value for the chosen test circuits, which proves that the proposal outperforms existing schemes.