FPGA-embedded optimization algorithm to maximize the acetate productivity in a dark fermentation process
This paper presents an optimization strategy to online maximize the acetate productivity rate in a dark fermentation (DF) process. The Golden Section Search algorithm is used to compute the maximum acetate productivity rate as a function of the inlet chemical oxygen demand (COD) and the dilution rat...
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Veröffentlicht in: | Journal of process control 2024-12, Vol.144, p.103323, Article 103323 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | This paper presents an optimization strategy to online maximize the acetate productivity rate in a dark fermentation (DF) process. The Golden Section Search algorithm is used to compute the maximum acetate productivity rate as a function of the inlet chemical oxygen demand (COD) and the dilution rate, selected as a manipulated variable. Such maximum productivity is considered as a reference by a Super-Twisting controller to regulate the real acetate productivity rate of the DF process. Due to the lack of sensors to measure the COD online, the optimization strategy includes an unknown input observation strategy integrated by a Luenberger observer interconnected to a Super-Twisting observer to estimate the inlet COD concentration. The optimization algorithm is embedded in an FPGA (Field Programmable Gate Array) device to minimize hardware resources and power consumption. The feasibility of the online optimization strategy embedded in an FPGA, using a digital architecture designed with a fixed-point format representation, is demonstrated by numerical simulations. Results show that the optimization strategy requires 53% of the logic elements and 100% of 8-bit multipliers of an FPGA Cyclone II and the power consumption estimated is only 190mW.
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•A model-based RTO strategy is proposed to maximize acetate production.•Golden section search and Super-Twisting controller are used as optimization strategy.•The state and the unknown input are estimated throughout a nonlinear observer.•The optimization strategy proposed is embedded in an FPGA device.•Feasibility of the optimization approach is demonstrated by closed-loop simulations. |
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ISSN: | 0959-1524 |
DOI: | 10.1016/j.jprocont.2024.103323 |