Robust corrective control against fundamental and non-fundamental mode attacks with application to an asynchronous digital system
This article presents a robust model matching corrective control scheme for input/state asynchronous sequential machines (ASMs) vulnerable to both fundamental and non-fundamental mode attacks. Specifically, when non-fundamental mode attacks occur, ASMs undergo unauthorized state transitions in their...
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Veröffentlicht in: | Information sciences 2024-03, Vol.661, p.120145, Article 120145 |
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Hauptverfasser: | , |
Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | This article presents a robust model matching corrective control scheme for input/state asynchronous sequential machines (ASMs) vulnerable to both fundamental and non-fundamental mode attacks. Specifically, when non-fundamental mode attacks occur, ASMs undergo unauthorized state transitions in their transient behaviors, reaching faulty states. The attack outcome is exacerbated if non-fundamental mode attacks occur during the procedure of model matching by the controller. We address the necessary and sufficient condition and design procedure for a state-burst-feedback corrective controller that eliminates the adverse effect of both fundamental and non-fundamental mode attacks, while matching the stable-state behavior of the closed-loop system to that of a reference model. To demonstrate the synthesis of the controller and applicability of the proposed scheme, a practical ASM termed the payload data manager and the corrective controller are implemented on field-programmable gate array (FPGA) circuits. Experimental results are provided on model matching and robust corrective control overcoming both fundamental and non-fundamental mode attacks.
•Asynchronous sequential machines vulnerable to cyber attacks.•Existence of both fundamental mode and non-fundamental mode attacks.•Model matching controller resilient against (non-)fundamental mode attacks.•Implementation of asynchronous digital systems with (non-)fundamental mode attacks.•Experimental verification on the FPGA circuit. |
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ISSN: | 0020-0255 1872-6291 |
DOI: | 10.1016/j.ins.2024.120145 |