A test vector selection method based on machine learning for efficient presilicon verification

•A test vector selection method is proposed to minimize CP verification redundancy.•Sequential pattern extraction method for critical point verification is proposed.•Great coverage can be accomplished by using a small test vector.•The proposed method significantly shortens presilicon verification time.•The proposed approach significantly outperforms other existing methods. Presilicon verification is a critical inspection process that detects errors in the circuit design of semiconductor chips early in the design process. Presilicon verification is performed by entering into the circuit simulation test vectors that can induce current to flow in the circuit to verify whether current flows at critical points (CPs). CPs are the major management points of the circuit. The current verification approach of randomly choosing a test vector and feeding it into the simulation is inefficient because verified CPs are often reverified. Moreover, certain CPs can be verified with a small number of test vectors. Finding a verifiable vector takes considerable time, leading to an increase in the time required for CP verification. In this study, we propose a test vector selection method that can verify as many CPs as possible with the minimum number of test vectors. Moreover, we propose contrast PrefixSpan, a sequential pattern mining (SPM) algorithm that extracts the sequential pattern used for CP verification. CPs can be verified with many fewer test vectors when test vectors input into the simulation are extracted using the proposed method than when test vectors are randomly selected, thereby shortening the presilicon verification time.