CMOS-compatible electrochemical nanoimprint: High throughput fabrication of ordered microstructures on semiconductor wafer by using a glassy carbon mold

•CMOS-compatible electrochemical nanoimprint lithography was developed by replacing the platinum (Pt) metallized imprint mold by a glassy carbon one.•The contaminants, i.e., the metal residuals and metal ions trapped in the fabricated microstructures, were avoided by designing a spatially separated corrosion cell.•The corrosion rate and machining efficiency was promoted and comparable to Pt electrocatalyst, dramatically higher than the carbon materials reported before. Metal assisted chemical etching (MACE), as an emerging wet chemical etching method for fabricating semiconductor micro/nano-structures (MNS), has attracted wide attentions because of the advantages of simple processes, high accuracy and no damages. However, the conventionally used noble metal catalysts (such as Au, Pt,) trapped in the micro/nano-structures are difficult to be removed or reused, not only harming the electronic performances of the CMOS devices but also increasing the fabrication cost. Here, we propose an electrochemical nanoimprint strategy by using a glassy carbon (GC) imprint mold. To overcome the poor electrocatalytic activity of GC, the GC imprint mold was connected to a Pt sheet in the cathodic chamber. To avoid the contaminations of metal and metallic cations in the fabricated MNS, the cathodic chamber was separated from the anodic one by a proton exchange membrane. By optimizing the technical parameters, including the contact pressure between GC imprint mold and GaAs wafer, the concentration of electron acceptor in the cathodic chamber, the imprinting time, etc., a remarkable corrosion rate of about 130 nm/min was achieved, comparable with that of platinum electrocatalyst. Furthermore, by using a GC imprint mold in the spatially separated corrosion cell, the contaminations caused by both the metal catalysts and metallic ions can be eliminated. Thus, this work provides a potential approach to the high throughput fabrication of CMOS-compatible semiconductor microdevices.