Improving the computational efficiency of lock-in algorithms through coherent averaging

The lock-in amplifier and coherent averaging, established techniques for processing periodic signals, are combined in a novel system. In this approach, the signal is first averaged coherently for a number of periods and then passed through a lock-in with moving average filter of a whole number of pe...

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Veröffentlicht in:Digital signal processing 2024-11, Vol.154, p.104693, Article 104693
Hauptverfasser: Oliva, Matías J., Veiga, Alejandro L., García, Pablo A., Spinelli, Enrique M.
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Sprache:eng
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Zusammenfassung:The lock-in amplifier and coherent averaging, established techniques for processing periodic signals, are combined in a novel system. In this approach, the signal is first averaged coherently for a number of periods and then passed through a lock-in with moving average filter of a whole number of periods as low-pass filter. Results match those obtained with traditional lock-in with moving average filter, but maximizing the number of cycles used for the coherent average significantly reduces the multiplications involved in the calculation. Any lock-in system with moving average filter can take advantage of these results. Particularly in this study, they are employed to nearly double the achievable clock frequency of a lock-in system implemented on a Cyclone V FPGA, taking it from 119.39 MHz to 216.54 MHz without the use of hardware embedded multipliers. •Lock-in amplifier and coherent averaging are combined in a novel system.•Under certain conditions, results are equivalent to classical lock-in amplification.•The proposed system reduces drastically the number of multiplications needed.•An FPGA implementation of the system is shown and validated.•An improvement on the clock frequency is achieved while saving DSP blocks.
ISSN:1051-2004
DOI:10.1016/j.dsp.2024.104693