FPGA-based online voltage/current swell segmentation and measurement
•Voltage-swell segmentation and measurement.•Online power-quality-disturbance detection and characterization.•Hardware-processing architecture portable to different FPGA platforms.•Fast detection and measurement of a voltage/current-swell time span.•Cubic spline interpolation and Otsu segmentation a...
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Veröffentlicht in: | Computers & electrical engineering 2023-04, Vol.107, p.108620, Article 108620 |
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Sprache: | eng |
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Zusammenfassung: | •Voltage-swell segmentation and measurement.•Online power-quality-disturbance detection and characterization.•Hardware-processing architecture portable to different FPGA platforms.•Fast detection and measurement of a voltage/current-swell time span.•Cubic spline interpolation and Otsu segmentation are implemented in an FPGA.
Power-signal distortion is one of the main problems industry faces since it is produced by the use of non-linear loads and environmental disturbances. Swells are among the most common electrical disturbances that cause low power quality (PQ) in electric-energy delivery systems. Different methodologies have been proposed to detect disturbances, and as one of the most common electrical disruptions, the monitoring of voltage/current swells is an essential task for opportune correction and increase of the electric-system PQ. Unfortunately, most of the proposed methods for PQ monitoring do not perform a measurement of the disturbance time span. Hence, in this work, a novel method for detecting and measuring the time-length of voltage/current swells through spline interpolation and Otsu segmentation, implemented in an FPGA, is proposed. Obtained results from signals generated through a computer model and acquired from real experimentation demonstrate that the proposed approach can measure swell disturbances in the electric voltage/current signal from a distribution system with high resolution and precision, performing the time-span measurement of a swell disturbance in 81.3 μs, with high certainty of up to 99.945%. Furthermore, the portability of the proposed hardware processing unit is shown by its implementation in FPGA devices from two different vendors. |
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ISSN: | 0045-7906 1879-0755 |
DOI: | 10.1016/j.compeleceng.2023.108620 |