Social learning discrete Particle Swarm Optimization based two-stage X-routing for IC design under Intelligent Edge Computing architecture

One of the core features of Intelligent Edge Computing (IEC) is real-time decision making, therefore low delay is more important for IC design under IEC architecture. And in very large scale integration routing, wirelength is one of the most important indexes affecting the final delay of the IC design. Therefore, this paper introduces the X-routing with more potential for wirelength optimization and the Steiner Minimum Tree (SMT), which is the best routing model in multi-terminal nets. Then, based on Particle Swarm Optimization (PSO) technique which has the strong global optimization ability in Soft Computing, an effective Two-Stage X-routing Steiner minimum tree construction algorithm is proposed. The proposed algorithm is divided into two stages: social learning discrete PSO searching and wirelength reduction. In the first stage, two excellent strategies are proposed to maintain a good balance between exploration and exploitation capabilities of the PSO technique: (1) Chaotic decreasing inertia weight combined with mutation operator is set to enhance the exploration capability. (2) A new social learning approach combined with crossover operator is designed to ensure the diverse evolution of the swarm while maintaining the exploitation capability. In the second stage, a strategy based on local topology optimization is proposed to further reduce the length of X-routing Steiner tree. Experiments show that the proposed algorithm can achieve the best wirelength optimization and has a strong stability, especially for large-scale SMT problem, so as to better satisfy the demand of low delay of IC design under IEC architecture. [Display omitted] •Better satisfying the high-performance requirement for IC design under IEC.•Being divided into two stages to obtain routing scheme with shortest wirelength.•Presenting a novel Social Learning DPSO method for SMT problem.•Being validated with benchmark circuit suite.