Electronic properties of the Poly(3-hexylthiophene) / MoS2interfaces: The influence of the substrate

[Display omitted] •Characterization of the basal plane of MoS2 for a monocrystal and a CVD one by XPS and UPS.•Investigation of the P3HT growth and the electronic properties of P3HT/ MoS2 interface.•Schematic representation of the energy level diagram of the interface.•Determination of the hole barr...

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Veröffentlicht in:Applied surface science 2022-01, Vol.572, p.151372, Article 151372
Hauptverfasser: Drivas, Charalampos, Iacovella, Fabrice, Deligeorgis, George, Kennou, Stella
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Sprache:eng
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Zusammenfassung:[Display omitted] •Characterization of the basal plane of MoS2 for a monocrystal and a CVD one by XPS and UPS.•Investigation of the P3HT growth and the electronic properties of P3HT/ MoS2 interface.•Schematic representation of the energy level diagram of the interface.•Determination of the hole barrier and interface dipole. Since the isolation of graphene, layered semiconducting materials, such as graphene oxide and molybdenum disulfide (MoS2), have been used in flexible electronics interfaced with organic semiconductors. The knowledge of their interfacial properties is in progress as it is crucial for device optimization. In this study, we have investigated the electronic properties of the interfaces between MoS2 and in-situ thermally deposited P3HT by photoelectron spectroscopies. For the MoS2 substrates, a cleaved natural single crystal was used, as well as after in situ heating, and a CVD prepared MoS2 in order to investigate the effect of the different preparation methods on the electronic structure. To investigate the interfacial properties, the P3HT was deposited stepwise in-situ, up to 7 nm, and after each step, the interface was examined by XPS and UPS. The P3HT was found to be aligned vertically to the MoS2 basal plane. The interface energy diagrams are depicted, resulting in a hole barrier of 0.4 eV and an interface dipole of 0.7 eV. In the case of the CVD prepared MoS2 gap states have been observed which affect the device performance and they should be taken into consideration.
ISSN:0169-4332
1873-5584
DOI:10.1016/j.apsusc.2021.151372